FIG. 1 is a block diagram showing a conventional semiconductor memory device. FIG. 2 is a timing diagram of a reading operation for the conventional semiconductor memory device shown in FIG. 1. Referring to FIG. 1, a memory cell array 100 includes a plurality of blocks (not shown), each of which includes a plurality of rows, a plurality of columns, and a plurality of memory cells. Each of the plurality of memory cells are formed at the intersections between the plurality of columns and the plurality of rows. The rows and columns include a plurality of word lines and bit lines, respectively. For example, the memory cells and the word lines in a dynamic random access memory (DRAM) device are organized in accordance with a hierarchical word line scheme that is well known to those skilled in the art. The word lines may be divided into sub-word lines and main word lines wherein a proportion of the main word lines to the sub-word lines is 1:y (y is an integer number).
A row address buffer 110 receives external addresses An (n is an integer) having a TTL (transistor-transistor logic) voltage level. The addresses An are synchronized with a row address strobe RAS signal, and generates row addresses RAm (m is an integer) having a CMOS (Complementary Metal Oxide Semiconductor) voltage level as shown in FIG. 2. A row predecoder 120 decodes the row addresses RAm provided from the row address buffer 110. A block selecting circuit 130 generates a first selection signal BLSk as the block selection-information (e.g., DRA0 and DRA1) of the row addresses Ram are decoded by the row predecoder 120. A row decoder 140 selects and drives a row related to the first selection signal BLSk. A second selection signal DCAij selects one of rows in the selected block. As a result, respective voltage levels on a pair of bit lines BL and BLB, as depicted in FIG. 2, are developed in accordance with data (e.g., logic `1` or logic 0) stored in an addressed memory cell.
Furthermore, when the row address strobe RASB signal is activated, a master clock generating circuit 160 generates a master clock PRD as a pulse signal. The phase of the master clock PRD is complementary to the row address strobe RASB signal. A sensing control signal generating circuit 170 generates a sensing control signal PS. The sensing control signal PS indicates a period when a sensing operation of the addressed memory cell is performed. A sensing enable signal generating circuit 180 generates two complementary sensing enable signals LANG and LAPG. Thus, a sense amplifier(s) (not shown in FIG. 1) in a bit line precharge/sense amplifier circuit 230 is enabled by the sensing enable signals LANG and LAPG. The sense amplifier(s) senses the voltage levels on a pair of the developed bit lines BL and BLB and to amplify the sensed voltage levels into power supply voltage Vcc and ground voltage Vss or into ground voltage Vss and power supply voltage Vcc in accordance with data stored in the addressed memory cell.
The semiconductor memory device 1000 depicted in FIG. 1, includes a plurality of column selection lines (not shown). The column selection lines may be organized in accordance with the hierarchical column selection scheme. For example, the column selection lines may be divided into local column selection lines and global column selection lines. The proportion of the local column selection lines to the global column selection lines is 1:z (z is an integer).
Next, as shown in FIG. 2, when a column address strobe CASB signal changes from a low level to a high level, a column address buffer 190 receives the external addresses An having TTL voltage levels. The external addresses An are synchronized with the column address strobe CASB signal. The column address buffer 190 generates column addresses CA1 (1 is an integer) having a CMOS voltage level. A column main decoder 200 generates a first column selection signal DCA01 for selecting among the column addresses Ca1 (e.g., CA0 and CA1). A column predecoder 210 generates a second column selection signal DCAij as local selection information decoding other column addresses among the column addresses CA1.
A column decoder 220 selects a column selection line CSL (i.e., a local column selection line (not shown)), so that data sensed and amplified by the sense amplifier (not shown) is provided to corresponding input/output (I/O) lines through an I/O gating circuit 240 controlled by the column decoder 220.
As shown in FIG. 2, when the column address strobe CASB signal is disabled, signals CA1, DCAcd, DCA01, CSLx, and the like related to the column selection operation are disabled. When the row address strobe RASB signal is disabled, signals PRD, PS, LANG, LAPG, and the like related to the row selection operation are disabled. If the block selecting circuit 130 is inactivated, all the bit lines of the selected block of the semiconductor memory device 1000 are precharged to a predetermined level (e.g., 1/2 Vcc) because the precharge signal generating circuit 150 is activated by the first selection signal BLSk disabled in accordance to the row address strobe RASB signal.
According to the conventional semiconductor memory device 100 as described above, after the data stored in the addressed memory cell is output to the I/O lines (e.g., IO and IOB), a sensing operation related to the addressed memory cell continues to be performed because the sensing enable signals LANG and LAPG are enabled by the row address strobe RASB signal. By so operating, current continues to be consumed by the sense amplifier(s) in the bit line precharge/sense amplifier circuit 230 during the sensing operation until the row address strobe /RASB is disabled.